META SoC Processors

META™ multi-threaded processor architecture is targeted at complex SoC devices designed for global products that offer multi-function capability, requiring multiple high speed data stream I/Os and peripherals while meeting tough system timing, power and performance constraints.

With many competing demands on memory subsystems from multiple units including CPUs, DSPs, and GPUs, a processor's potential throughput is greatly reduced by SoC memory latency. Traditional CPU solutions struggle to manage this efficiently, often stalling for as much as 50% of the time, throwing away valuable processor bandwidth. Only a processor designed for maximum system latency tolerance can tackle this issue so prevalent in many of today’s SoCs – META provides the ideal solution.

The META processor architecture is specifically designed for high performance real time operation at low clock speeds, making the best possible use of memory bandwidth and providing exceptional tolerance of system latencies.

META hardware threads are each a virtual processor operating in a parallel / overlapped manner with no context switching overheads. Each thread can be RISC or DSP – which is decided during synthesis – and each virtual processor can run an independent OS, including Linux or Imagination's own MeOS RTOS – or they can run code natively. Read more at META SoC Processors.

The META IP core portfolio comprises three IP core families:

META HTP – High End
Highest performance, tuned for combined Linux + RTOS-based applications + DSP all on one common datapath

META MTP – Mid-Range
High performance, multi-threaded, but smaller footprint designed for advanced RTOS-based or native embedded applications

META LTP – Low End
Lightweight, ultra-small single threaded 32-bit microcontroller.

The scalable META architecture has all the benefits of multi-processing but with less silicon resource and development complexity. And it is significantly lower cost than a multi-processor approach. Its unified architecture delivers both powerful DSP and general-purpose processing whilst the multi-threading 'hides' memory latency in SoC solutions.